Area and energy optimized multilayer QCA-based 4N-bit scalable multiplier (M4N-MUL)
Department of ECE, ABES Institute of Technology, Ghaziabad, Uttar Pradesh, India
2 Department of ECE, SRM Institute of Science and Technology, NCR Campus, Ghaziabad, Uttar Pradesh, India
3 School of Computer Science Engineering and Technology, Bennett University, Greater Noida, Uttar Pradesh, India
Accepted: 14 November 2022
Published online: 27 November 2022
Quantum dot cellular automata-based combinational and sequential designs have been widely explored by the researchers in the last decade. It is a promising technique which have abilities to provide low power high speed digital logic circuits at nanoscale. A low power and area optimized array logic-based architecture of 4-bit multiplier is presented in this paper. The design procedure includes the development of an optimized ripple carry adder by the recreation of the design of an XOR gate. The designs are implemented over QCA designer 2.1.0 and QCA-pro to obtain performance cost in terms of number of cells, area, delay and power dissipation. The present work achieved a reduction of up to 57% in terms of area and 43% in terms of number of cells as compared to the prior reported QCA based multiplier designs. Energy calculation has also been performed to prove the efficacy of the work at different power levels. Moreover, the design can be scaled in the order of 4N at lower overheads that proves its novelty to the work reported in this area.
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