https://doi.org/10.1140/epjp/s13360-024-04901-0
Regular Article
A novel low-latency ALU in the one-dimensional clock scheme in QCA nanotechnology
1
Department of Electrical Engineering, Nour Branch, Islamic Azad University, Nour, Iran
2
Faculty of Engineering and Technology, University of Mazandaran, Babolsar, Iran
Received:
9
September
2023
Accepted:
15
January
2024
Published online:
1
February
2024
Quantum-Dot Cellular Automata (QCA) is a candidate alternative technology for CMOS technology in VLSI circuits in the post-transistor era. QCA can be implemented in molecular and nanoscale structures. In VLSI circuits, the Arithmetic and Logic Unit (ALU) is one of the most critical units, which is an optimal design with low latency is essential for better processing speed. In this paper, an ALU is designed based on the needs of the one-dimensional clock. The proposed ALU has only 1.5 clock cycles latency, supports 12 instructions, and uses 443 cells in three layers. In addition, all inputs and outputs are in the same layer to make connecting the proposed ALU to other blocks simpler. To achieve this latency and the one-dimensional clock capability, AND, OR, XOR gates are fully redesigned to work in the one-dimensional clock structure. The one-dimensional clock enables the design of the clock bed and QCABED separately. Besides the proposed ALU in this paper, design rules are also proposed for one-dimensional clock circuit designing. Proposed designs are confirmed by QCADesigner, a well-known QCA layout design, and verification tool. QCADesigner-E was used for power estimation.
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© The Author(s), under exclusive licence to Società Italiana di Fisica and Springer-Verlag GmbH Germany, part of Springer Nature 2024. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
