https://doi.org/10.1140/epjp/s13360-025-06668-4
Regular Article
A high-speed and low-cost approximate full adder in QCA technology
Department of Computer Architecture, Faculty of Computer Engineering, University of Isfahan, 8174673441, Isfahan, Iran
a
m.reshadinezhad@eng.ui.ac.ir
Received:
25
December
2024
Accepted:
17
July
2025
Published online:
4
August
2025
Researchers and designers should face the challenges caused by memory and energy limitations. Quantum-dot Cellular Automata (QCA) offers a promising alternative with its high speed and low power consumption for dense emerging nano-electronic structures. Applying the approximate computing paradigm, where lower hardware complexity is prioritized over complete accuracy, can reduce power consumption. Integrating approximate computing with QCA reduces energy consumption and enhances system performance, although at the potential cost of reduced accuracy. The arithmetic unit is responsible for binary addition, subtraction, and multiplication. This article proposes a methodology for integrating QCA-based gates with approximate computing to achieve high-speed computation while minimizing resource usage. Additionally, it introduces a novel high-speed and cost-efficient design for a QCA-based approximate full adder, demonstrating improved hardware evaluation metrics, including delay, energy consumption, and acceptable error margins. The cost analysis indicates that the proposed design effectively balances circuit design trade-offs, particularly regarding delay and area. The functionality validation of the proposed circuit is assessed by the QCADesigner-E tool. Compared to the state of the art, the proposed design enhances performance metrics, achieving average improvements of 50% in delay, 26% in the number of QCA cells, and 78% in cost. These advancements are significant for the development of efficient and cost-effective QCA-based systems. Various error evaluation metrics assess the proposed approximate full adder's computational accuracy across three implementation scenarios of the 8-bit approximate adder architecture. Application-level simulation outputs show that the proposed circuits perform well in all scenarios, with the Peak-Signal-to-Noise Ratio (PSNR) exceeding 30 dB.
Copyright comment Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
© The Author(s), under exclusive licence to Società Italiana di Fisica and Springer-Verlag GmbH Germany, part of Springer Nature 2025
Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
