https://doi.org/10.1140/epjp/s13360-023-04147-2
Regular Article
Complete depletion area in SOI junctionless FETs by multiple buried P-type pockets
Electrical Engineering Department, Semnan University, Semnan, Iran
Received:
15
September
2022
Accepted:
31
May
2023
Published online:
14
June
2023
This paper describes a unique approach for calculating the complete depletion area in silicon-on-insulator (SOI) junctionless FETs (JL-FET). The suggested approach significantly reduces the OFF-current (IOFF) by utilizing several P-type pockets at the channel's bottom. Using calibrated simulations, the recommended device exhibits a substantial ION/IOFF ratio of 5 × 105, decreased DIBL and subthreshold slope, and an accurate ON-current (ION) value at accumulation modes. By using our approach and generating a larger depletion area, we reduce the gate capacitance (CG) and the gate–drain capacitance (CGD). The suggested structure's electrical properties exhibit encouraging results compared to a conventional device, and DC and RF effects have been explored.
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© The Author(s), under exclusive licence to Società Italiana di Fisica and Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
