Eur. Phys. J. Plus (2015) 130: 80
https://doi.org/10.1140/epjp/i2015-15080-x

Regular Article

Effects of series and parallel resistances on the C-V characteristics of silicon-based metal oxide semiconductor (MOS) devices

¹ Laboratory of Composite Ceramic and Polymer Materials (LaMaCoP), Sfax Faculty of Science, Soukra Road Km 4, 3038, Sfax, Tunisia
² Departments of Physics, Faculty of Sciences of Sfax, Sfax, Tunisia

^* e-mail: omarrejieba@yahoo.com

Received: 30 December 2014
Revised: 21 March 2015
Accepted: 27 March 2015
Published online: 28 April 2015

Abstract

This paper investigates the electrical behavior of the Al/SiO₂/Si MOS structure. We have used the complex admittance method to develop an analytical model of total capacitance applied to our proposed equivalent circuit. The charge density, surface potential, semiconductor capacitance, flatband and threshold voltages have been determined by resolving the Poisson transport equations. This modeling is used to predict in particular the effects of frequency, parallel and series resistance on the capacitance-voltage characteristic. Results show that the variation of both frequency and parallel resistance causes strong dispersion of the C-V curves in the inversion regime. It also reveals that the series resistance influences the shape of C-V curves essentially in accumulation and inversion modes. A significant decrease of the accumulation capacitance is observed when R _s increases in the range 200–50000 Ω. The degradation of the C-V magnitude is found to be more pronounced when the series resistance depends on the substrate doping density. When R _s varies in the range 100 Ω–50 kΩ, it shows a decrease in the flatband voltage from −1.40 to −1.26 V and an increase in the threshold voltage negatively from −0.28 to −0.74 V, respectively. Good agreement has been observed between simulated and measured C-V curves obtained at high frequency. This study is necessary to control the adverse effects that disrupt the operation of the MOS structure in different regimes and optimizes the efficiency of such electronic device before manufacturing.