Numerical simulation of analog metrics and parasitic capacitances of GaAs GS-GAA FinFET for ULSI switching applications
Department of Applied Physics, Delhi Technological University, Delhi, India
Accepted: 6 December 2021
Published online: 12 January 2022
This paper explores the efficacy of Gallium Arsenide (GaAs) as a fin material on the analog metrics and parasitic capacitances of Gate Stack Gate-All-Around (GS-GAA) FinFET. Besides, capacitance-related parameters such as gain–bandwidth product (GBP) and transconductance frequency product (TFP) are also evaluated to analyze the device switching and DC performance. The simulated results validate that compared to Si, GaAs as a fin material increases the switching (Ion/Ioff) ratio by ∼ 103 times and reduces the leakage current, DIBL, and SS by ∼ 99%, ∼ 50%, and ∼ 26%, respectively. Moreover, for GaAs, the peak value of GBP and TFP increases by 9.93 and 11.40 times compared to Si due to the considerable decrease in the parasitic capacitances. Thus, replacing Si with GaAs as a fin material significantly improves the short-channel effects (SCEs) of the device (Ioff, DIBL, and SS) and capacitances-related parameters (Cgs, Cgd, Cgg, GBP, and TFP). Besides, the impact of gate length (Lg), fin height (HFin), and fin width (WFin) of GaAs GS-GAA FinFET on analog metrics and parasitic capacitances are assessed for low power ULSI switching applications. The simulated results reveal that the SCEs and parasitic capacitances improve considerably with decreased Lg, HFin, and WFin.
© The Author(s), under exclusive licence to Società Italiana di Fisica and Springer-Verlag GmbH Germany, part of Springer Nature 2022