https://doi.org/10.1140/epjp/s13360-023-04758-9
Regular Article
A capacitance model for threshold voltage computation of double-insulating fully-depleted silicon-on-diamond MOSFET
Faculty of Engineering, Shahrekord University, Shahrekord, Iran
Received:
5
August
2023
Accepted:
29
November
2023
Published online:
18
December
2023
In this paper, we present a capacitance model for 22 nm double-insulating (DI) fully-depleted (FD) silicon-on-diamond (SOD) MOSFET near the threshold voltage. The model takes into account the capacitance coupling between the front- and back-gate to the source/drain layers through the diamond layer, the second insulating layer (SiO2), and the substrate. The second insulating layer is located on top and partially covers the diamond layer, serving to enhance device electrostatics and enable a heat spreading mechanism from the device’s active region through the diamond layer. The effects of substrate depletion capacitance and the length and thickness of the second insulating layer are incorporated into the model as corresponding capacitances. Surface potentials in the silicon layer of the transistor are calculated, and a strong inversion condition is applied. Using the capacitance model, we compute the front- and back-gate threshold voltages and compare them with those obtained from TCAD simulations. The results from the analytical solutions and device simulations are promising, exhibiting good agreement in terms of gate oxide thickness, silicon film thickness, buried diamond layer thickness, second insulating layer thickness, and length. We observe an 8 mV variation in the front-gate threshold voltage and a 20 mV difference in the back-gate threshold voltage when the length of the second insulating layer is changed from 22 to 102 nm, considering a silicon film thickness of 5 nm. For a second insulating layer length smaller than 40 nm, the perpendicular source/drain capacitance to the back body has the most significant influence on the back channel. Conversely, for a second insulating layer length greater than 60 nm, the co-planar source/drain capacitance to the back body dominates. Overall, the capacitance model provides valuable insights into the impact of the second insulating layer length on the threshold voltage of the DI FD SOD MOSFET.
Copyright comment Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
© The Author(s), under exclusive licence to Società Italiana di Fisica and Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
