https://doi.org/10.1140/epjp/s13360-025-06772-5
Regular Article
Design of an efficient nanoscale reversible arithmetic and logic unit using quantum dots for energy-efficient digital signal processing devices
School of Intelligence and Electronic Engineering, Dalian Neusoft University of Information, 116023, Dalian, China
Received:
9
July
2025
Accepted:
18
August
2025
Published online:
20
September
2025
Digital signal processing (DSP) plays a vital role in real-time analysis and transformation of signals, supporting biomedical, wireless communication, image processing, and control systems. In nanotechnology, DSP is an essential part of interfacing sensors, doing image processing, collecting data from nanodevices, and performing high-speed calculations in compact environments. In response to the demand for increased processing speeds while minimizing physical area and power consumption, traditional computing architectures are now significantly constrained. The arithmetic and logic unit (ALU) is the most important part of signal processing and computational systems, carrying out arithmetic and logic operations as well as additions and subtractions. On the nanoscale level, DSP ALUs are required to be very efficient, have low power consumption, and use minimum physical area. According to Landauer's concept, conventional ALUs designed utilizing complementary metal–oxide–semiconductor (CMOS) technology are made to be permanent, wasting a significant amount of energy and also losing information while operating. To handle these problems, the latest developments suggest an ALU architecture that can be reversed and constructed using quantum dot cellular automata (QCA) nanotechnology. This design applies a coplanar reversible full adder that is built with the Haghparast and Navi Gate (HNG) and modified Fredkin (MF) gates to make the main part of the ALU. The suggested ALU in nanotechnology delivers a desirable improvement in this performance. Simulation results show a decrease in cell count, an increase in area efficiency, and a decrease in latency of 16.37%, 44.59%, and 41.17%, respectively, which places it among the smallest and fastest reported QCA-based ALU designs to date. These developments can greatly optimize DSP architectures, resulting in more energy-efficient, faster nanoelectronic systems needed to support future high-performance computing systems. The suggested design is not just simpler hardware, but it also enhances the promise of QCA-based circuits to scalable nanoelectronic integration in emerging technologies.
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© The Author(s), under exclusive licence to Società Italiana di Fisica and Springer-Verlag GmbH Germany, part of Springer Nature 2025
Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
